7.3: Dynamic Behavior of CMOS Inverter

The values of $V_H,V_L$ don't affect CMOS power delay, but are primarily affected by other parameters like ${\tau }_P$, the propogation delay of the inverter.

7.3.1: Propagation Delay Estimate

We look to estimate the propogation delay using our capacitance approximation:

These conditions are the same conditions we used to determine ${\tau }_{PHL}$ for the NMOS resistor with a resistive load. Using the equations from Modules 7 & 8 - MOSFET Layout and Capacitances, NMOS inverter-dynamic characteristics#^adda20, we can say that:

for a CMOS where $V_H=2.5V$ and $V_{tn}=0.6V$ then:

a similar analysis on the other state gives that:

Notice that since $K_P<K_n$ often, then we have that ${\tau }_{PHL}>{\tau }_{PLH}$. Hence, we usually use our smallest design where $W/L=2/1$ so then $(W/L{)}_N=2/1$ while say $(W/L{)}_P=5/1$ or something similar.

Thus only when ${\tau }_{PLH}=\tau PHL$ (which is ideal in most circumstances), then:

7.3.2: Rise and Fall Times

Use the same table from Modules 7 & 8 - MOSFET Layout and Capacitances, NMOS inverter-dynamic characteristics#^adda20, we get:

7.3.3: Performance Scaling

When we change some capacitance or $W/L$ for a CMOS, we have to consider the change in ${\tau }_P$ or similar:

where all the ref values are our initial values, and anything with a ${}^{\prime }$ indicates a change to a new variable.

7.3.4: Delay of Cascaded Inverters

Consider:

Here the first inverter acts as expected, but for the delay times for the other 4 inverters are significantly slower:

thus, when inverters are stacked like this we expect just two propagation delays total (doubled ${\tau }_P$).

7.4: Power Dissipation and Power Delay Product in CMOS

7.4.1: Static Power Dissipation

CMOS's have zero static-power dissipation, as they only drain power when switching (when idle, no power is lost). But in low power or high performance designs, static power is huge.

One way to deal with this is via:

The $M_{SA}$ and $M_{SB}$ control the power to logic blocks, where power to inactive blocks can be controlled via software or hardware control.

7.4.2: Dynamic Power Dissipation

As the gate charges and discharges load capacitance $C$ at frequency $f$, the power dissipation is equal to:

Usually $P_D$ is the largest component of power dissipation in CMOS gates at high enough frequencies. See 6.10 for specifics on where this equation comes from.

Here in 7.17 we see how, because of finite time in switching speed, we get a power loss ($P=IV$) from the time the CMOS switches. If we have a fast enough frequency, we see that the time plot we get has closer peaks (and more multiples of them).

7.4.3: Power Delay Product

We defined the power-delay product before in Modules 1 & 2 - NMOS Review#^86a3c7:

here $P_{av}=P_D=C{V}_{DD}^{2}f$. But $f=1/T$ is related to the rise and fall times of our CMOS:

as seen in Figure 7.18. For the highest possible switching frequency we have $t_a,t_b\to 0$ and the rise and fall times are the greater proportion (80%) of total transition time. Assuming $t_r=t_f$ then:

a lower bound on the power-delay product for CMOS is:

thus for better power we want to reduce $C$, but more so importantly $V_{DD}$ when possible.