4.1: Characteristics of MOS Capacitor

MOSFETs typically act like MOS Capacitors:

So the capacitance of the MOSFET is a non-linear function of voltage. Here:

• (a) shows the accumulation region, where the large negative charge on the metallic gate is balanced by positively charged holes attracted to the Si-Si dioxide interface below the gate
• (b) shows the depletion region, where the hole density near the surface is reduced below the majority-carrier level set by the substrate doping level.
• (c) shows the inversion region, where enough positive charge on $V_g$ creates negative charges on the top layer of the $n$ well, creating the $n$-type inversion layer.

4.5: Capacitances in MOS Transistors

The capacitances of our MOSFETs will limit the switching speed of our MOS. There's four primary capacitances:

4.5.1: Triode Region $C$

First, the total gate-channel capacitance $C_{ox}^{″}$ dependent on the area of the gate:

Meyer's model of this splits the capacitance based on gate-source and gate-drain capacitances:

The gate-source and gate-drain overlap capacitances $G_{GSO},G_{GDO}$ come from the small overlap fringes between the gate-source and gate-drain regions.

There's the source-bulk and drain-bulk capacitances $C_{SB},C_{DB}$ between the $pn$ junctions in the MOSFET:

here $C_J$ is the junction bottom capacitance, and $C_{JSW}$ is the junction sidewall capacitance. Notice that this equation just takes proportions of each based on how important they are to the capacitance. Here $A_S,A_D$ are the areas of the drain and source respectively.

4.5.2: Saturation Region $C$

4.5.3: Capacitance in Cutoff

since the conducting channel is now gone, so $C_{GC}$ goes away.

In cutoff a small capacitance $C_{GB}$ appears between gate and bulk terminal:

Giving:

where $C_{GBO}$ is the gate-bulk capacitance per unit length.

You'll see that all these equations will depend on:

• Region of operation
• The voltages applied to the terminals

4.6: MOSFET Modeling in SPICE

The following is the circuit SPICE uses to simulate a MOSFET:

It tabulates the following values:

SPICE will use the equations we've used before to find drain current, but SPICE also uses the following for the capacitances:

6.11: Dynamic Behavior Of MOS Logic Gates

We now consider the time aspect of gates! We'll calculate, based on MOSFET values, values like rise and fall time, propogation delay.

6.11.1: Capacitances of Logic Circuits

As we've seen above, there's a LOT of MOS capacitances to keep track of. So we'll lump a lot of them together:

We'll use an effective capacitance $C$ instead. We won't find $C$ in terms of all the $C_{GSO},C_{GBO},...$ but we will assume that we have some estimate for $C$.

As we add more gates, like we see above, then $C$ increases, and temporal responses will decreases as a result.

We can estimate our load capacitance $C_L$ as:

where $C_{out}$ is the capacitance looking into the output of the gate, $C_{in}$ is the capacitance looking into the gate, and $C_W$ is the capacitance of the wiring connecting one gate to the next, and $FO$ is the fanout. Thus:

where the factor of 2 comes from the voltage change across $GD3$ is twice the input logic swing.

6.11.2: Dynamic Response of the NMOS Inverter w/ Resistive Load

Calculating $t_r$ and ${\tau }_{PLH}$ for a resistive load, when off we have a RC circuit when $V_I$ turns off, and thus the inverter makes $V_O$ slowly high as an RC time constant to charge to $V_H=V_{DD}$. For a simple RC network:

A similar analysis finds $t_f$ and ${\tau }_{PHL}$, but this calculation is much more complicated since the NMOS goes from saturation to triode region (whos equations themselves between the states will be approximations anyways), so a good approximation is to use $I_D>>I_R$ and then notice a pure exponential decay is a fairly good approximation:

As such, then:

giving:

6.11.3: Psuedo NMOS Inverter

For the high-to-low transient, we actually get the same calculations for ${\tau }_{PHL}$ and $t_f$ as above, as we assume $I_{DL}<<I_{DS}$:

For low-to-high, we actually get a similar version, except we care about the on resistance of the $L$ MOSFET instead:

where:

6.11.4: Final Comparison of NMOS Inverter Delays

Instead of deriving other MOSFET inverter times, we can just compare some:

We note that NMOS MOSFETS typically switch "faster", hence the transition to NMOS technology rather than PMOS.

6.11.5: Scaling Based Upon Reference Circuit Simulation

When we move smaller and smaller, a lot of our simpler assumptions about MOSFETS start to break down. For scaling, the size of the device needs to increase proportionally. So, to choose new propogation delays or not we do:

6.11.6: Ring Oscillator Measurement of Intrinsic Gate Delay

Constructing a ring of inverters creates an artificial clock (ie: ring oscillator) of an odd number of inverters, with period $T$ as:

where ${\tau }_{P0}$ is the average propagation delay of the unloaded inverter.

6.11.7: Unloaded Inverter Delay

Without a load:

so:

so it's ideal to have a small inverter length, as well as large $V_{DD}$, but this is only an approximation ignoring the output capacitance.