Modules 5 & 6 - Psuedo-NMOS Inverter, CMOS Inverter-Static Characteristics

Most of these notes continue from the end of Modules 3 & 4 - NMOS Inverters & PMOS Review#6.6.3 NMOS Inverter w/ Depletion-Mode Load and prior. Read up on that if you're lost.

6.6.4: Static Design of the Pseudo NMOS Inverter

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This circuit is known as the pseudo NMOS since circuit operation is similar to that of NMOS logic, even though it is usually in CMOS designs we'll see later.

For our purposes we'll use the same $I_{D D} = 80 μ A, V_{D D} = 2.5 V, V_{L} = 0.2 V$ values from prior.

Calculation of $(W / L)_{P} = (W / L)_{L}$ and $(W / L)_{S}$ .

For the $M_{L}$ PMOS we have $V_{G S} = - 2.5 V$ and thus the transistor is in the conducting state, so since $V_{D S} = 0.2 V - 2.5 = - 2.3 V$ and $V_{G S} - V_{t p} = - 2.5 V - (- 0.6 V) = - 1.9 V$ , so we'll have saturation:

I_{D} = \frac{K_{p}^{'}}{2} (W / L)_{P} \cdot (V_{G S} - V_{t p})^{2} \Rightarrow 80 μ A = 0.5 \cdot 40 \frac{μ A}{V^{2}} \cdot (W / L)_{P} \cdot (- 2.5 - (- 0.6)^{2}) V^{2}

giving:

(W / L)_{P} = \frac{1.11}{1}

For the other $(W / L)_{S}$ , we need $V_{H}$ . Using Figure 6.24b, as before we have $M_{L}$ in the saturation state. When $V_{I} = V_{L} = 0.2 V$ we have $M_{S}$ as off, so current flows through the PMOS to charge the output node until $V_{D S}$ of the transistor collapses to zero, so $V_{H} = V_{D D}$ .

Thus, the calculations for $(W / L)_{S}$ are similar as to those in Modules 3 & 4 - NMOS Inverters & PMOS Review#6.5.2 Design of the $W / L$ Ratio for $M_{S}$ , so see that section for more information.

Noise Margin Analysis for Pseudo NMOS Inverter

Finding $V_{I L}, V_{O H}$ first, we need a relationship between $V_{I}, V_{o}$ . We guess when $V_{I} = V_{I L}$ we have $M_{S}$ in the saturation region and that $M_{L}$ will be in the triode. This is because we are in some states between the $M_{L}$ being totally cutoff, and $M_{S}$ is in a similar boat. One being in cutoff isn't super interesting, so it's better when both aren't just in cutoff, and one is in a different state than the other (as otherwise the voltages just get scaled).

Thus:

K_{S} / 2 \cdot (V_{I} - V_{t n})^{2} = K_{L} (- V_{D D} - V_{t p} - \frac{V_{o} - V_{D D}}{2}) (V_{o} - V_{D D})

we care when the slope $\frac{\partial V_{o}}{\partial V_{i}} = - 1$ , so do the derivative. We solve for $V_{o}$ instead since it's easier to extract, and actually find when the reciprocal is -1 (which is the same as the normal derivative). Giving:

V_{I} = V_{t n} + \frac{1}{\sqrt{K_{R}}} \sqrt{(2 (V_{D D} + V_{t p}) - (V_{D D} - V_{o})) (V_{D D} - V_{o})}, K_{R} = \frac{K_{S}}{K_{L}}

the derivative is tedious and gives:

V_{I L} = V_{t n} + \frac{V_{D D} + V_{t p}}{\sqrt{K_{R}^{2} + K_{R}}}

and:

V_{O H} = V_{D D} - (V_{D D} + V_{t p}) (1 - \sqrt{\frac{K_{R}}{K_{R} + 1}})

you can calculate values and check that our assumptions were actually right the whole time. A similar process finds $V_{I H}, V_{O L}$ , where we flip and assume that $M_{L}$ is in saturation and $M_{S}$ is in triode. Doing a similar process gives:

V_{O L} = \frac{V_{D D} + V_{t n P}}{\sqrt{3 K_{R}}}

and:

V_{I H} = V_{t n} + \frac{2 (V_{D D} + V_{t p})}{\sqrt{3 K_{R}}} = V_{t n} + 2 V_{O L}

7.1: CMOS Inverter Technology

CMOS requires both a PMOS and NMOS together on one IC subtrate.

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Note, there's an implied diode between the $n$ -well and $p$ -type substrate. Thus, we need it to be reverse biased all the time, via using good connections of $V_{D D}$ and $V_{S S}$ .

The connections above create the following circuit diagram:

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The generic way it works is that if the NMOS is on, the PMOS is off. If the PMOS is on, the NMOS is off. Thus, we create an open on one side, giving rise to $V_{o}$ becoming either $V_{D D}$ or $V S S, g n d$ . In the intermediary, there will be time where both are on, creating the undefined region we've seen with previous inverter circuits.

One interesting thing is that the bodies of both transistors are connected to their respective sources, so $V_{S B} = 0 V$ so there is no body effect.

For this we'll use the following values:

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Note that:

Usually $V_{T O N} = - V_{T O P}$ .
$K_{n}^{'} = μ_{n} C_{o x}^{″}$ and $K_{p}^{'} = μ_{p} C_{o x}^{″}$ . So why are the $K$ values above not equal? Hole mobility in a PMOS is about 40% of the hole mobility in that of an NMOS, hence the difference.
Thus, $V_{t n} = V_{T O N}$ and $V_{t p} = V_{T O P}$ .

One way to layout the substrate is via:

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7.2: Static Characteristics for CMOS Inverter

Consider the following:

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First, consider when $v_{I} = 2.5 V$ . Then $V_{G S} = 2.5$ for the NMOS, and $V_{G S} = 0 V$ for the PMOS. For the NMOS $V_{G S} > V_{t n} = 0.6 V$ so a channel exists in the NMOS. But the PMOS is off since $V_{G S} = 0$ . So in (a), the capacitor $C$ discharges through the NMOS and $v_{o} \to 0 V$ , until there's not any current through $M_{N}$ , and no current goes through $M_{P}$ .

Once $V_{I}$ is set to $0 V$ , then $V_{G S} = 0 V$ for the NMOS so it's off. For the PMOS $V_{G S} = - 2.5 V$ so a channel exists. $C$ gets charged from the 2.5V supply connected to $M_{P}$ . Once steady-state is reached, $M_{N}$ and $M_{P}$ have no current through since the NMOS is off.

Note that $V_{H} = V_{D D}$ and $V_{L} = 0 V$ . Also the logic swing $Δ V = 2.5 V$ , and the static power dissipations is zero, as the DC current is zero (eventually) in both logic states.

7.2.1: CMOS Voltage Transfer Characteristics

We have 5 regions:

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Note that the boundary between region 2 and 3 (and 3 and 4) is defined by the triode/saturation regions of operation. Saturation in $P$ occurs when:

2.5 - V_{o} \geq 2.5 - V_{I} - V_{T O P} \Rightarrow V_{O} \leq V_{I} + V_{T O P}

similarly we can find the other line equation for when $M_{N}$ enters saturation:

V_{o} \geq V_{I} - V_{T O N}

when $K_{p} = K_{n}$ then we get that $V_{M} = \frac{V_{D D}}{2}$ . But when $K_{p} \neq K_{n}$ , then it shifts away from this value. Recall that we defined $K_{R} = \frac{K_{n}}{K_{p}}$ .

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Using the figure, when $K_{R} > 1$ then we move the $V_{M}$ to the left, and vice verse for $K_{R} < 1$ .

A nice thing about CMOS inverters is that they can operate at low voltages, where we've gotten as low as $V_{D D} = 2 V_{T} \ln (2)$ , which can get as low as $40 m V$ .

7.2.2: Noise Margins for CMOS

Finding $V_{I H}$ . For $V_{I}$ near this value, we assume that PMOS is saturated and NMOS is in triode, giving:

K_{n} (V_{I} - V_{t n} - \frac{V_{o}}{2}) V_{o} = \frac{K_{p}}{2} (V_{I} - V_{D D} - V_{t p})^{2}

we can simplify this to:

K_{R} (2 V_{I} - V_{t n} - V_{o}) = (V_{I} - V_{D D} - V_{t p})^{2}

solving for $V_{o}$ gives an equation we can take the derivative of and set it to -1, giving our value for $V_{I H}$ :

V_{I H} = \frac{2 K_{R} (V_{D D} - V_{t n} + V_{t p})}{(K_{R} - 1) \sqrt{1 + 3 K_{R}}} - \frac{V_{D D} - K_{R} V_{t n} + V_{t p}}{K_{R} - 1}

V_{O L} = \frac{(K_{R} + 1) V_{I H} - V_{D D} - K_{R} V_{t n} - V_{t p}}{2 K_{R}}

for when $K_{R} = 1$ :

V_{I H} = \frac{5 V_{D D} + 3 V_{t n} + 5 V_{t p}}{8}, V_{O L} = \frac{V_{D D} - V_{t n} + V_{t p}}{8}

The whole $V_{I L}$ process is the exact same, except the PMOS is in triode and NMOS is in saturation:

V_{I L} = \frac{2 \sqrt{K_{R}} (V_{D D} - V_{t n} + V_{t p})}{(K_{R} - 1) \sqrt{K_{R} + 3}} - \frac{(V_{D D} - K_{R} V_{t n} + V_{t p})}{K_{R} - 1}

and:

V_{O H} = \frac{(K_{R} + 1) V_{I L} + V_{D D} - K_{R} V_{t n} - V_{t p}}{2}

and when $K_{R} = 1$ :

V_{I L} = \frac{3 V_{D D} + 5 V_{t n} + 3 V_{t p}}{8}, V_{O H} = \frac{7 V_{D D} + V_{t n} - V_{t p}}{8}

use the $N M$ equations after getting these values via Week 1 - nMOSFET and Inverter Characteristics#^64d3d1 and similar.

6.6.4: Static Design of the Pseudo NMOS Inverter

Calculation of (W/L)P=(W/L)L and (W/L)S.

Noise Margin Analysis for Pseudo NMOS Inverter

7.1: CMOS Inverter Technology

7.2: Static Characteristics for CMOS Inverter

7.2.1: CMOS Voltage Transfer Characteristics

7.2.2: Noise Margins for CMOS

Calculation of $(W / L)_{P} = (W / L)_{L}$ and $(W / L)_{S}$ .