Modules 14 & 15 - RAM and Static Storage Elements, Dynamic Storage Elements

8.1.2: A 256-Mb Memory Chip

A 256-Mb chip is separated into 8 32-Mb subarrays
Memory address is selected by column and row address decoders
Row decoders and wordline drivers bisect each 32Mb subarray
Each 32-Mb subarray is further subdivided into 16 2-Mb sections, each with 16-blocks of 128Kb.
The 128 Kb is the basic building block of this array.

There's $M$ bits of row address, and $N$ bits of column address, giving $M + N$ -bit addresses with a total of $2^{(} M + N)$ possible addresses/storage locations. In the picture, the sense amplifiers help read and write the information of the selected memory cells.

When a row is selected, all 127 bits are all accessed in parallel for a word. These are wordlines and the data in vertical columns are called bitlines. The column address can extract each specific bit if needed.

8.4: Sense Amplifiers

8.7:

8.3: Dynamic Memory Cells

Power applied to static memory is required to refresh their memory/data from losing charge. But smaller memory cells can also be built, known as dynamic memory.

8.3.1: The One-Transistor Cell

This is a 1-T cell:

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We have a $C_{c}$ cell capacitor that stores the data. Leakage currents exist in the drain-bulk and source-bulk junctions of the transistor, and in the transistor channel. Periodically, cell data is written back to keep the desired cell voltages. This is the refresh operation. Each storage cell in a DRAM usually must be refreshed every 2 to 10 ms.

8.3.2: Data Storage in the 1-T Cell

A 0 is represented by $0 V$ and a 1 is represented by a high level on $C_{c}$ . Writing occurs by putting the desired voltage level onto the bitline and turning on access to the $M_{A}$ transistor.

Storing a 0

In this case, the bitline is a 0, and the bitline terminal of the MOSFET acts as the source of the MOSFET. The gate is raised to $V_{D D} = 3 V$ . If the cell voltage is already zero, then ,the drain-source voltage is 0, so the current is 0. If the cell has a 1 with $v_{c} > 0$ then the MOSFET completely discharges $C_{c}$ to give a 0.

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Storing a 1

In this case, the bitline is a 1, and the bitline terminal acts as a drain. If the gate gets raised to $V_{D D}$ then:

If there was previously a 1 then no current flows like in the previous case.
If there was a 0, then $V_{D S} > 0$ so then we have current from the left to the right, charging $C_{c}$ to some $v_{c}$ . Really, this charging is almost instant (dependent on $M_{A}$ ) so essentially it hits the desired vol

Because $V_{D S} = V_{G S}$ and since $M_{A}$ is an enhancement mode device, $M_{A}$ will operate in saturation.

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Notice that:

V_{c} = V_{G} - V_{t n} = V_{G} - (V_{T O} + γ (\sqrt{V_{c} + 2 ϕ_{F}} - \sqrt{2 ϕ_{F}}))

Notice here body effect is good since it reduces $V_{c}$ and hence reduces power draw of the 1-T.

8.3.3: Reading Data from the 1-T Cell

We first precharge the bitline to a known voltage, usually $V_{D D}$ or half of it. The access transistor $G$ is turned on, and charge sharing occurs between $C_{B L}$ and $C_{c}$ .

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We get that:

Q_{I} = C_{B L} V_{B L} + C_{c} V_{c}

after closing, the current equalizes the voltage across the two capacitors (no current will eventually flow, so no voltage drop over the MOSFET). Hence:

Q_{F} = (C_{B L} + C_{c}) V_{F}

Thus:

V_{F} = \frac{C_{B L} V_{B L} + C_{c} V_{c}}{C_{B L} + C_{c}}

The signal to be detected the change in the voltage on the bitline, so then:

Δ V = V_{F} - V_{B L} = \frac{C_{c}}{C_{B L} + C_{c}} (V_{C} - V_{B L}) = \frac{(V_{C} - V_{B L})}{\frac{C_{B L}}{C_{c}} + 1}

Typically we have $C_{B L} >> C_{c}$ , since we want a large enough $Δ V$ to detect, implying that:

V_{F} \approx V_{B L}

so when we read (closing the switch), we'll accidentally destroy the data we had on there. Hence, we must write-back any data we read. The sense amplifier helps read the voltage change $Δ V$ .

8.4.2: A Sense Amplifier for the 1-T Cell

See the figure below for a simple sense-amplifier:

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The stages are:

Precharge Phase: