Modules 11 & 12 - Static Dual Logic & Dynamic Domino Logic

6.9: Complex NMOS Logic Design

A big use of MOS logic over other forms is to combine NAND and NOR gates into complex configurations. This brings us to complex logic gate design.

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Here the given NMOS logic gate has $Y = \overset{―}{A + B C + B D} = \overset{―}{A + B (C + D)}$ .

This is commonly an AND-OR-INVERT (AOI) gate. The AND terms are created by stacking two transistors vertically, then placed in parallel to form the OR function:

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But notice we have to change the sizing of our transistors when we combine in this way.

When placed in series, we double our length $L$ , so to compensate we double $W / L$ for each transistor $M_{C}, M_{D}$ , or just even it out with our other set of transistors.
When placed in parallel, we double our width $W$ , so to compensate we half $W / L$ for each transistor, or just even it out with the other set of transistors.

Thus, to transistor size:

Method 1: Find the worst-case path:
- Ex: see path $C D B$ in the circuit above with 3 transistors. Make each 3 times the size of the reference switching transistor to make an equivalent on-resistance similar to $M_{S}$ in the reference inverter. So each should get $6.66 / 1$ .
- In the second path, $M_{A}, M_{B}$ , we want the sum of the on-resistance of the devices to be equal to the on-resistance of $M_{S}$ in the reference inverter:

\frac{R_{o n}}{(W / L)_{A}} + \frac{R_{o n}}{(W / L)_{B}} = \frac{R_{o n}}{(W / L)_{S}} \Rightarrow \frac{R_{o n}}{(W / L)_{A}} + \frac{R_{o n}}{6.66} = \frac{R_{o n}}{2.22} \Rightarrow (W / L)_{A} = 3.33

Method 2: Partition into subnetworks
- Ex: $M_{B}$ is in series with network $M_{A C D}$ so set their $W / L$ as equal. Then repeat for the smaller network $M_{A}$ compared with $M_{C D}$ . Since $M_{C}, M_{D}$ are in series then they need the same $W / L$ (use so then $(W / L)_{B} = 2 (2.22 / 1) = 4.44 / 1$ and so then $(W / L)_{A}$ is $4.44 / 1$ and $(W / L)_{C} = (W / L)_{D} = 8.88 / 1$

Comparing areas between the two designs gives the second with $28.5 F^{2}$ and the first with $25.1 F^{2}$ , so the first is preferred (you can calculate by adding up all $W / L$ ratios)

7.5: CMOS NOR and NAND Gates

CMOS NOR Gate

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The way this works as shown in (b) is that:

The output is low when input $A$ or input $B$ is high, because NMOS A is On and NMOS B is on, so then the voltage at Y is shorted (0V) so its low. Notice that in a similar manner PMOS A is Off and the same is for the other PMOS
In general, a parallel path in an NMOS network can be reconfigured to a series path in PMOS, and vice versa

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Transistor Sizing

We consider the worst possible input conditions. When $A B = 10$ or $01$ we have transistor $A$ or $B$ capable of discharging through capacitor, so we need the NMOS as the same size as the reference inverter. The PMOS part only conducts when $A B = 00$ and they're two PMOS in series, so the same on-resistance as the reference requires both $W / L$ ratios be doubled as then it halves each PMOS on resistance.

Body Effect

While during switching body effect plays a role, all PMOS source drain nodes are at $V_{D D}$ and at $V_{S S}$ if instead NMOS. So the on-resistance of the PMOS isn't affected by body effect, only during transient.

Two-Input NOR Gate Layout

An example is shown below:

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Three-Input NOR Gate

The same analysis occurs for a 3-input NOR gate:

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Here, the output is low when $A$ or $B$ or $C$ is conducting, so we fail to have that when $A B C = 000$ which turns on all the PMOS. All NMOS inverters are again $2 / 1$ for the on-resistances (from reference), and instead we need to multiply by $3$ for each PMOS to get it's actual $W / L$ for the same reasons.

We use a shorthand symbols for Two-Input CMOS NOR gate:

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CMOS NAND Gates

We can do a similar process for NAND gates and get:

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The PMOS are in parallel and need the reference $5 / 1$ as before seen, as when they are both on they will give that on resistance. The $N M O S$ are both doubled in $W / L$ for similar reasons as mentioned above.

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For the multi-input gate above, it's the same story. All PMOS stay the same, while the NMOS get multiplied by however many inputs we have.

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7.6: Design of Complex Gates in CMOS

We look at a single example of CMOS logic gate design. We'll design a CMOS logic gate implementing $Y = \overset{―}{A + B C + B D}$ .

First, we know that $Y = \overset{―}{A + B (C + D)}$ and $\bar{Y} = A + B (C + D)$ . We use the same logic network we used in Figure 6.34 above:

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We don't know the topology of the PMOS switch network, and the W/L ratios of those PMOS. First, we construct a graph of the NMOS network:

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Each note in the network corresponds to the node in the graph. Each arc is one of the transistors. Then we use this graph to construct the PMOS network. First, place a new node inside of every enclosed path:

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Then, add an arc cut through the NMOS arcs and connect the pairs of nodes that are separated by NMOS arcs. The related PMOS get's the same label as the NMOS:

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This network is the PMOS network we are looking for:

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Lastly, we need to find the $W / L$ ratios for all PMOS. Look for the worst-case path in the NMOS. Here, it's the two transistors in series $M_{C}, M_{B}$ or $M_{D}, M_{B}$ . As such then $M_{C}, M_{B}$ need to be twice as large as the reference, which also carries over to $M_{D}$ , while $M_{A}$ is just the reference in case of when it is on and need to discharge a capacitive load.

For the PMOS, it's a similar story. For the worst case of PMOS, it's $A C D$ , so those need to be 3 times as large as the reference. Then $B$ needs to be:

\frac{R_{o n}}{15 / 1} + \frac{R_{o n}}{(W / L)_{B}} = \frac{R_{o n}}{5 / 1} \Rightarrow (W / L)_{B} = 7.5 / 1

7.7: Minimum Size Gate Design and Performance

The way our network works for CMOS, we get one NMOS and one PMOS transistor for each logic input variable. There's also:

area penalties
tradeoff between logic delay and area penalty (more delay can be traded in for less area)

In the NMOS switching network for our designed CMOS circuit, we had a worst-case path of two transistors in series, with $W / L = 2 / 1$ so an equivalent $R_{o n} = 1 / 1$ using the compared reference inverter. So then $τ_{P H L} = 2 τ_{P H L I}$ . For the PMOS, there's three transistors in series, two in parallel, yielding an effective $W / L$ ratio of $2 / 3$ , giving:

τ_{P L H} = \frac{5 / 1}{2 / 3} τ_{P L H I} = 7.5 τ_{P L H I}

The average propagation delay of this gate then is:

τ_{P} = \frac{2 τ_{P L H I} + 7.5 τ_{P L H I}}{2} = 4.75 τ_{P L H I}

we sometimes want to have Euler Paths instead, that go through each transistor once and only once.

7.8: Dynamic Domino CMOS Logic

Dynamic logic uses precharge and evaluation phases governed by a system clock to elmininate DC current that occurs in single-channel static logic gates; however, logical outputs are only valid during a portion of the evaluation phase of the clock. A domino CMOS is based on a signle clock signal:

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Operation starts when clock is low, where $M_{N C}$ is off. This turns off the path to ground to $F$ , and also pulls $M_{P C}$ node 4 to logic high and forcing the inverter output to low.

When the clock goes high, the capacitance at 4 is discharged, and if a conducting path exists through $F$ , so $F = 1$ , then node 4 is discharged to 0. If $F = 0$ then no discharge happens, and the node 4 voltage is high, so output is still low.

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Notice that functional evaluation during the positive clock phase ripples through the gates like a series of dominos - hence the name of domino logic.

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