14: RAM and Static Storage Elements

3

a

We know that:

So then:

b

Do the same thing:

4

Since half the bits are the only thing that have power loss when restored, we have 1-Gbit which is $2^{30}$ bits. Hence:

44

Consider the logic functions for:

Here our inputs are 01 ports respectively:

• If we 00, then $Q$ and $\overline{Q}$ retain whatever state they were in previously.
• If we 01, then $\overline{Q}$ is set to high, so $Q$ is set to low (reset input)
• If we 10, then $Q$ is set to high, so $\overline{Q}$ is set to low (set input)
• If we 11, then we have an unstable state.

Hence this is just a standard RS-Flip Flop. Here the 0 port acts as a set, and 1 acts as a reset.

45

Consider:

Here, we want an RS-Flip Flop.

Regenerative switching of the cell will take place when the voltage at Q is pulled low enough
by transistor M R that the voltage at Q rises above the NMOS transistor threshold voltage.
Equating drain currents for this condition yields the value of VQ . It appears that
the NMOS transistor will be in the linear region, and the PMOS transistor will be saturated.
For VDD = 5V, 4x10−5
2
4
1


 

 5 − VQ − 0.7( )2
= 10−4 2
1


 

 VQ − 0.7 − 0.7
2


 

0.7 → VQ = 2.64V which agrees with
the assumptions. Now, M R must be large enough to force VQ = 2.64V. M R and the PMOS
load transistor are both in the linear region.
4x10−5 4
1


 

 5 − 0.7 − 0.7 − 2.36
2


 

2.36 ≤ 10−4 W
L


 

 R
5 − 0.7 − 2.64
2


 

2.64 → W
L


 

 R
≥ 1.16
1

15: Dynamic Storage Elements

9

Consider:

Here we have a $V_{BL}=2.5V$ and $V_{WL}=2.5V$.

a

For a bit of 0, here, the right side acts as a drain, so $V_{GS}=2.5V$. Note that:

Hence $V_{OV}=1.9V$. Hence, current will totally flow from the drain to the source (right to left) as we always have positive $V_{OV}$. So $V_{CL}=0$.

For a bit of 1, here, the left side acts as the drain, so $V_{GS}=2.5V-V_C$. Here:

which is our high bit voltage.

b

What $V_{GS}$ allows $V_C=2.5V$ for a 1? If we want this, then we need to be in CO, so then $V_{OV}\le 0$. We know that:

Thus:

So then:

12

Assume that $C_{BL}>>C_C$, so then:

So then:

So then:

so then:

If a 128Mb memory is refreshed every 5ms:

15

Consider:

When we have logic 1, then $V_{WL}=0.0V$. No current flows since the left acts as the source, so $V_{SB}=0V$ and $V_{SG}=0V$. As such, then since $V_{BL}=3.3V$ then $V_C=3.3V$.

For logic 0, we have $V_{BL}=0V$ and $V_{WL}=0V$. The right acts like a source. Since $V_C=0V$ at that point then:

If instead we have $V_{DD}=2.5V$ then still logic high is 2.5V while logic low is given by: