HW 7 - Transition Gates and Multiplexers

116

We can calculate $V_{O V}$ as:

\begin{aligned} V_{t n} & = V_{T O N} + γ (\sqrt{V_{S B} + 2 ϕ_{F}} - \sqrt{2 ϕ_{F}}) \\ = 0.75 V + 0.5 \sqrt{V} (\sqrt{V_{I} + 0.6 V} - \sqrt{0.6 V}) \end{aligned}

Worst case for the NMOS is when $V_{O V} = 0 \Rightarrow V_{G S} = V_{t n} \Rightarrow 2.5 V - V_{I} = V_{t n}$ as when that happens we are at the lowest of triode (essentially $R_{o n, n}$ ):

2.5 - V_{I} = 0.75 V + 0.5 \sqrt{V} (\sqrt{V_{I} + 0.6 V} - \sqrt{0.6 V}) \Rightarrow 1.426 V

When this happens then $R_{o n, n} \to \infty$ so look at the PMOS resistance:

250 Ω = R_{o n, p} = \frac{1}{K_{p}^{'} (W / L)_{P} (V_{S G} - | V_{t p} |)} = \frac{1}{40 μ A / V^{2} \cdot (W / L)_{P} (1.426 V - V_{t p})}

We need to find $V_{t p}$ here:

V_{t p} = 0.75 + 0.5 (\sqrt{2.5 - 1.426 + 0.6} - \sqrt{0.6}) = 1.010 V

Thus:

(W / L)_{P} = \frac{1}{250 Ω \cdot 40 μ A / V^{2} \cdot (1.426 V - 1.010 V)} = 240

Thus:

(W / L)_{P} = 240 / 1

Repeat the process:

\begin{aligned} V_{t p} & = 0.75 + γ (\sqrt{2.5 - V_{I} + 0.6 V} - \sqrt{0.6 V}) \\ = V_{I} \end{aligned} \Rightarrow V_{I} = 1.0743 V

thus:

V_{t n} = 0.75 + 0.5 (\sqrt{1.0743 + 0.6} - \sqrt{0.6}) = 1.010 V

(W / L)_{N} = \frac{1}{250 Ω \cdot 100 μ A / V^{2} \cdot (2.5 V - 1.0743 V - 1.010 V)} = 96.2

so then:

(W / L)_{N} = 96.2 / 1

117

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a

For the first transistor, we'll need:

V_{t n} = 0.70 V + 0.6 (\sqrt{2.5 - V_{t n} + 0.6 V} - \sqrt{0.6 V}) \Rightarrow V_{t n} = 1.087 V

So then $V_{S} = 2.5 V - 1.087 V = 1.413 V$ since there's no current going through any FETs, so then if it was in triode then $V_{D S} = 0 V$ which would contradict $V_{G S} \geq V_{t n}$ . As such then that FET is in saturation.

For the second transistor notice that we are in triode. This is because now we have:

V_{t n} = 0.70 V + 0.6 (\sqrt{1.413 V - V_{t n} + 0.6 V} - \sqrt{0.6 V}) \Rightarrow V_{t n} = 0.803 V

But this is a contradiction since then $V_{G S} = 0.803 V$ so then $V_{S} = 1.7 V$ which is too much for a voltage drop. Hence we have triode so then $V_{D S} = 0 V$ so then $V_{S} = 1.413 V$ . The third transistor follows the same logic. Hence, since $V_{S} > V_{M}$ then the inverter outputs $V_{L}$ .

For (b) notice that $V_{S G} = 2.5 V$ so then we are definitely not in CO. Here $I = 0$ so then since $V_{S B} = 0 V$ then we have $V_{t p} = V_{T O P} = - 0.7$ . So $V_{O V} = 1.8 V$ . Notice $V_{S G} \neq | V_{t p} |$ therefore since $I = 0$ we cannot be in saturation. Therefore, we are in triode, so then $V_{S D} = 0 V$ therefore, all the FETs carry the 2.5V signal through. Hence the inverter outputs $V_{L}$ .

b

For this one, these are just three "switches" connected in series to the inverter, where no voltage drop occurs (since we have $V_{D D}$ as an input here). Essentially you force triode over all the FETS, so then the inverter input just gets $V_{D D}$ , which it turns into $V_{L}$ .