P 7.97, 103, 105

Static Dual Logic

61

64

65

70

The worst case occurs by looking at the longest PMOS and NMOS network path, and dividing the number of transistors over the overall range of $W/L$.

For PMOS:

$(W/L{)}_{ACD}=(15/1)/3=5/1$

and for NMOS:

$(W/L{)}_{BC}=(W/L{)}_{BD}=(4/1)/2=2/1$

Thus for $V_{DD}=2.5V$:

and:

Thus $\boxed{{\displaystyle {\tau }_P=3.94\text{ ns}}}$.

Using $t_r=t_f=3{\tau }_P=11.8\text{ ns}$.

73

a

The device implements $Y=\overline{(A+B)(C+D)(E+F)}$.

b

c

When all NMOS are on, then we get an effective 3 transistors in series (worst-case) and two in parallel, giving:

d

For the PMOS we get 3 transistors now in parallel, and 2 in series, giving:

Domino Logic

97

103

We're given:

a

Assuming all $A_i=0$ from the circuit, then going into the evaluate phase (clock when high), while we have assumed that $C_i$'s are still uncharged (as we just entered the phase). If $A_0=1$ at this moment, then the voltage at node $B$ has charge sharing between $C_1,C_2$ (as the $A_0$ related MOS becomes a short, connecting the tops of $C_1$ and $C_2$).

Thus we can use:

Thus for $V_B$:

Where we know that $V_1$ prior to the switch must be $V_{DD}$ as it's uncharged, and similar for $V_2=0V$. As such:

Hence $V_B$ is two- thirds of the $V_{DD}$.

b

Now when $A_1=1$ is changed then we get a similar scenario, where since $C_3=C_2$ then our total capacitance is now 4 times as large. Hence we get charge sharing over all capacitors. Here $V_1=V_2=\frac{2V_{DD}}{3}$ and $V_3=0V$ as before so then we get:

so then the voltage gets halved.

c

In the worst case we have our case from (b) (notice if all are on we get that the capacitor just discharges), hence we need to have $C_1/C_2$ be such that:

105