HW 5 - CMOS Inverter Dynamic and Power Energy Characteristics
7.3: CMOS Inverter Dynamic Characteristics
1
We can find the and via:
and similar for the PMOS. Here , and we have :
and:
24
a
We know that:
and:
where here . Notice that:
and:
Thus:
therefore by symmetry. Furthermore:
b and c
The same calculations apply, just change and respectively:
then:
and for c:
then:
27
Use the same formula as prior:
thus:
so:
and:
29
Again just use the same formula:
by the symmetry of as well as then we'll have :
then:
31
For simplicity, let's design a symmetrical CMOS inverter, so we want . We also require this since we want . Then:
where is a placeholder for either as the process is the same for both. Thus:
7.4: CMOS Power Characteristics
43
a
Each gate can get:
b
If then:
47
a
Here:
so then . At (peak current) we have both 's in saturation:
Giving:
Plugging back in:
b
Doing the same process:
Giving:
Plugging back in:
51
Here and . We solved this problem in HW 5 - CMOS Inverter Dynamic and Power Energy Characteristics#24. By the symmetry of the 's and the 's then our rise and fall times and similar were similar. Here:
If , using for the first, for the second, and for the latter:
52
a
Again, just use the value from HW 5 - CMOS Inverter Dynamic and Power Energy Characteristics#29:
b
The highest switching frequency is when , so then:
so since then so then .
c
At this highest frequency: