HW 3 - Psuedo-NMOS Inverters and CMOS

6: Pseudo-NMOS Inverters

6.90

Consider the pseudo NMOS inverter below:

Pasted image 20240128182216.png

We are given:

K_{n}^{'} = 100 \frac{μ A}{V^{2}}, K_{p}^{'} = 40 \frac{μ A}{V^{2}}, V_{t n} = 0.6 V, V_{t p} = - 0.6 V

Rather now $V_{L} = 0.25 V$ . We'll need to change our width-length ratios as a result. Consider when $V_{I} = V_{H}$ . Then on the switching MOSFET (ie: the NMOS) we have it that $V_{G S} = 2.5 V$ so then $V_{o} = V_{H} = V_{L} = 0.25 V$ . We assume $(W / L)_{P}$ stays the same.

$V_{D S} = 0.25 V$ on the $M_{S}$ , while it is $V_{G S} = 2.5 V$ , so then $V_{G S} - V_{t n} = 1.9 V$ so then we are in triode for the NMOS. Since $I_{D}$ in the spec stays unchanged, we can assume $I_{D} = 80 μ A$ , so then:

\begin{aligned} I_{D} & = K_{n} (W / L)_{s} \cdot (V_{G S} - V_{t n} - 0.5 V_{D S}) V_{D S} \\ \Rightarrow 80 μ A & = 100 μ A / V^{2} \cdot (W / L)_{s} \cdot (1.9 V - 0.5 \cdot 0.25 V) \cdot 0.25 \\ \Rightarrow (W / L)_{s} = 1.803 / 1 \end{aligned}

Now consider the noise margins $N M_{L}$ and $N M_{H}$ . We can first find all $V_{I L}, V_{I H}, V_{O L}, V_{O H}$ . We note that:

K_{R} = \frac{K_{S}}{K_{L}} = \frac{180.3}{44.4} = 4.061

So we can use our equations:

V_{I L} = 0.6 V + \frac{2.5 V + - 0.6 V}{\sqrt{{4.061}^{2} + 4.061}} = 1.02 V

V_{O L} = \frac{2.5 V - 0.6 V}{\sqrt{3 \cdot 4.061}} = 0.544 V

So then:

N M_{L} = V_{I L} - V_{O L} = N M_{L} = 0.476 V

and then:

V_{I H} = 0.6 V + \frac{2 (2.5 V - 0.6 V)}{\sqrt{3 \cdot 4.061}} = 1.689 V

V_{O H} = 2.5 V - (2.5 V - 0.6 V) (1 - \sqrt{\frac{4.061}{4.061 + 1}}) = 2.302 V

thus:

N M_{H} = V_{O H} - V_{I H} = 0.613 V

6.95

We'll design an NMOS inverter to operate from $V_{D D} = 1.8 V$ and $V_{L} = 0.2 V$ with a power of $P = 100 μ W$ . We assume $V_{t n} = 0.5 V$ and $V_{t p} = - 0.5 V$ .

We'll choose to use the Pseudo NMOS inverter design. First, let's get $I_{D}$ :

P = V_{D D} \cdot I_{D} \Rightarrow I_{D} = \frac{P}{V_{D D}} = \frac{100 μ W}{1.8 V} = 55.56 μ A

we also can assume from the table that $K_{n}^{'} = 100 μ A / V^{2}$ and $K_{p}^{'} = 40 μ A / V^{2}$ .

Now we consider when $V_{I} = V_{H} = 1.8 V$ , and then $V_{o} = 0.2 V$ . Notice for $M_{L}$ that then we get that $V_{G S} = - 1.8 V$ (always) and $V_{D S} = 0.2 - 1.8 = - 1.6 V$ so then $V_{S G} - | V_{t p} | = 1.3 V$ so then $V_{S D} > V_{S G} - | V_{t p} |$ so we are in saturation:

55.56 μ A = 20 μ A / V^{2} \cdot (W / L)_{L} \cdot (1.3 V)^{2}

so then we get that $(W / L)_{L} = 1.64 / 1$ .

Moving to the $M_{S}$ , we care about the triode state, which occurs when $V_{I} = V_{H} = 1.8 V$ and $V_{o} = V_{H} = 0.2 V$ , and we can check that $V_{D S} = 0.2 V$ , $V_{G S} = 1.8 V$ so then $V_{D S} < V_{O V} = 1.3 V$ . Thus:

55.56 μ A = 100 μ A / V^{2} \cdot (W / L)_{S} \cdot (1.3 - 0.5 \cdot 0.2) 0.2 \Rightarrow (W / L)_{S} = 2.315 / 1

Now for the noise margins. We can use the equations derived for us:

K_{p} = \frac{K_{s}}{K_{L}} = \frac{2.315 \cdot 100 μ A / V^{2}}{1.64 \cdot 40 μ A / V^{2}} = 3.529

V_{I L} = 0.5 V + \frac{1.8 V - 0.5 V}{\sqrt{{3.529}^{2} + 3.529}} = 0.825 V

V_{I H} = 0.5 V + \frac{2 (1.8 V - 0.5 V)}{\sqrt{3 \cdot 3.529}} = 1.300 V

V_{O L} = \frac{1.8 V - 0.5 V}{\sqrt{3 \cdot 3.529}} = 0.400 V

V_{O H} = 1.8 V - (1.8 V - 0.5 V) (1 - \sqrt{\frac{3.529}{3.2529 + 1}}) = 1.648 V

Thus:

N M_{L} = V_{I L} - V_{O L} = 0.425 V, N M_{H} = V_{O H} - V_{I H} = 0.348 V

7.15

Consider the following circuit:

Pasted image 20240130103536.png

This is a Pseudo NMOS. We'll find $V_{H}$ and $V_{L}$ for this gate. Consider when we $V_{I} = V_{H}$ , then we get $V_{o} = V_{L}$ .

a

Notice for the top $M_{p}$ PMOS that $V_{G S} = - 3.3 V$ so then assuming using the value $V_{t p} = - 0.6 V$ then $V_{S G} - | V_{t p} | = 2.7 V$ no matter our state. Clearly $3.3 V - V_{L} = V_{S D} > V_{O V}$ so then we'll be in saturation no matter what. Furthermore, in this state for $M_{L}$ NMOS we have $V_{G S} = V_{H}$ and $V_{D S} = V_{L}$ , and since $V_{G S} - V_{t n} = V_{H} - 0.6 V > V_{L} = V_{D S}$ then $V_{D S} < V_{O V}$ so then we are in triode.

So then equate the currents:

\frac{40 μ A / V^{2}}{2} (1 / 1) (2.7 V)^{2} = K_{n}^{'} (5 / 1) (V_{H} - 0.6 V - 0.5 (V_{L})) V_{L}

We can assume that $V_{H} = 3.3 V$ since when $V_{I} = V_{L}$ and vice versa we have $M_{N}$ is off, so then $V_{H} = V_{D D} = 3.3 V$ as there's no current running through the PMOS (so it's in triode and $V_{D S} = 0 V$ ):

\Rightarrow 0.2916 V^{2} = V_{L} (2.7 V - 0.5 V_{L}) \Rightarrow V_{L} = 0.110 V

Notice that plugging in these values into our $M_{N}$ analysis from above, we get the expected saturation results, and our assumption for $V_{H}$ still remains valid as

b

Repeat but with $V_{D D} = 2.5 V = V_{H}$ . We yield the same conclusions:

\Rightarrow 0.1444 V^{2} = V_{L} (1.9 - 0.5 V_{L}) \Rightarrow V_{L} = 0.078 V

And our saturation assumptions are correct once again.

c

Repeat but with $V_{D D} = 1.8 V = V_{H}$ :

\Rightarrow 0.0576 V^{2} = V_{L} (1.2 - 0.5 V_{L}) \Rightarrow V_{L} = 0.049 V

Again we still have $V_{H} - 0.6 V = 1.2 V > V_{L} = 0.049 V$ for our saturation assumption.

7: CMOS Inverters

7.2

We draw the cross section for a CMOS process using a $p$ -well rather than an $n$ -well:

7.5

Consider the following circuit:

Pasted image 20240130121657.png

Here we say $V_{D D} = 2.5 V$ and $V_{S S} = 0 V$ . We'll find $V_{H}, V_{L}$ for this inverter.

a

This is a standard CMOS inverter circuit. We know that $V_{H} = V_{D D} = 2.5 V$ , as given when we have a $V_{I} = V_{L}$ , of which $V_{o} = V_{H}$ so then $M_{N}$ is off, and then $M_{P}$ is in triode, no current flows, so then $V_{H} = V_{D D}$ .

But when $V_{I} = V_{H}$ then $V_{o} = V_{L}$ . Here, we get the same scenario, except roles are switched. Now $M_{P}$ is off, and $M_{N}$ is on but no current flows. As such, then $V_{o} = V_{L} = - V_{S S} = 0 V$ , so $V_{L} = 0 V$ .

b

We have the same reasoning and get $V_{H} = 1.8 V$ and $V_{L} = 0 V$ .

7.11

We have a CMOS inverter such that $K_{n} = K_{p}$ . Use $V_{D D} = 2.5 V$ and $V_{t n} = 0.6 V, V_{t p} = - 0.6 V$ .

a

When $K_{n} = K_{p}$ then $K_{R} = 1$ so then we have just that $V_{M} = \frac{V_{D D}}{2} = 1.25 V$ .

b

If we are given that $V_{o} = V_{i}$ then we know that each $V_{o} = V_{I} = V_{M} = 1.25 V$ . Further, we are given $(W / L)_{N} = 2 / 1$ . We know that for the NMOS that $V_{G S} = 1.25 V$ and likewise $V_{D S} = 1.25 V$ , notice that $V_{G S} - V_{t n} = 0.55 V < V_{D S}$ so then we are in saturation. For the PMOS, we have it that $V_{S G} = 1.25 V$ and $V_{S D} = 1.25 V$ so then still the PMOS likewise is in saturation:

K_{p}^{'} / 2 \cdot (W / L)_{P} \cdot (1.25 V - 0.6 V)^{2} = K_{n}^{'} / 2 \cdot (W / L)_{N} \cdot (1.25 V - 0.6 V)^{2}

which then implies that $(W / L)_{N} = (W / L)_{P} = 2$ as expected. We can use our assumed value that $K_{n} = 100 μ A / V^{2}$ to get:

I_{D} = 50 μ A / V^{2} \cdot 2 \cdot (1.25 V - 0.6 V)^{2} = 42.25 μ A

c

We repeat (a). Notice now that $K_{n} = 2.5 K_{p}$ , so then since $K_{R} = \frac{K_{n}}{K_{p}}$ then we have $K_{R} = 2.5$ . We know, as our prior reasoning implied from (b), that since we are at $V_{I} = V_{o} = V_{M}$ then we are in saturation for both:

K_{p} / 2 \cdot (V_{D D} - V_{M} - | V_{t p} |)^{2} = K_{n} / 2 \cdot (V_{M} - V_{t n})^{2}

giving:

(2.5 V - V_{M} - 0.6 V)^{2} = 2.5 (V_{M} - 0.6 V)^{2} \Rightarrow V_{M} = 1.104 V

d

We can do the same analysis as we had done before:

I_{D} = 50 μ A / V^{2} \cdot 2 \cdot (1.104 V - 0.6 V)^{2} = 25.40 μ A

7.16

We need to find $V_{M}$ for a minimum size CMOS inverter where both $(W / L)_{N} = (W / L)_{P} = 2$ , if $V_{D D} = 2.5 V$ and $V_{t n} = - V_{t p} = 0.6 V$ . We can assume that $K_{p}^{'} = 40 μ A / V^{2}$ and $K_{n}^{'} = 100 μ A / V^{2}$ . Thus, at $V_{M}$ we have saturation in both:

20 μ A / V^{2} \cdot 2 \cdot (2.5 V - V_{M} - 0.6 V)^{2} = 50 μ A / V^{2} \cdot 2 \cdot (V_{M} - 0.6 V)^{2}

Simplifying:

\Rightarrow V_{M} = 1.104 V

7.17

From HW 3 - Psuedo-NMOS Inverters and CMOS#7.16, we find the $N M_{L}$ and $N M_{H}$ . We know that $K_{R} = 2.5$ in this case:

V_{I H} = \frac{2 \cdot 2.5 (2.5 V - 0.6 V - 0.6 V)}{(2.5 - 1) \sqrt{1 + 3 \cdot 2.5}} - \frac{2.5 V - 2.5 \cdot 0.6 V - 0.6 V}{2.5 - 1} = 1.220 V

V_{O L} = \frac{(2.5 + 1) V_{I H} - 2.5 V - 2.5 \cdot 0.6 + 0.6 V}{2 \cdot 2.5} = 0.174 V

V_{I L} = \frac{2 \sqrt{2.5} (2.5 V - 0.6 V - 0.6 V)}{(2.5 - 1) \sqrt{2.5 + 3}} - \frac{(2.5 V - 2.5 \cdot 0.6 V - 0.6 V)}{2.5 - 1} = 0.902 V

V_{O H} = \frac{(2.5 + 1) V_{I L} + 2.5 V - 2.5 \cdot 0.6 V + 0.6 V}{2} = 2.378 V

Thus:

N M_{L} = V_{I L} - V_{O L} = 0.728 V

N M_{H} = V_{O H} - V_{I H} = 1.158 V

7.22

Consider the following circuit:

Pasted image 20240130125837.png

We are given that all $(W / L)_{P} = 40 / 1$ and $(W / L)_{N} = 20 / 1$ for PMOS and NMOS. We need to find the current $I$ as shown above. We assume $V_{t n} = - V_{t p} = 0.6 V$ .

First, what will help is finding the $V_{O}$ connecting current between both CMOS inverters.

For the NMOS transistors, we have $V_{G S 1} = 0 V$ so $V_{O V 1} = - 0.6 V$ , implying that $M_{N 1}$ is in cutoff, so we can ignore it. For $M_{N 2}$ we have the opposite, where $V_{G S 2} = 2.5 V$ so $V_{O V 2} = 1.9 V$ . Let's assume that $V_{D S} < V_{O V 2}$ so then $M_{N 2}$ is in triode.

Notice that for the $M_{P n}$ transistors that we have $V_{S G 1} = 2.5 V$ and likewise $V_{S G 2} = 0 V$ . Notice then that $V_{S G 2} - | V_{t p} | = - 0.6 V$ so clearly $M_{P 2}$ is in cutoff and can be ignored. $V_{O V 1} = 1.9 V$ , so to have $V_{S D} < V_{O V 1}$ we'll assume that $V_{S D} = 2.5 - V_{O} < 1.9 V$ so then $V_{O} > 0.6 V$ which fits our range. In that case, then $M_{P 1}$ should be in triode:

Thus, equate the currents:

I_{P 1} = I_{N 2} \Rightarrow K_{p} \cdot (2.5 V - V_{o}) (2.5 V - 0.6 V - 0.5 (2.5 V - V_{o})) = K_{n} \cdot V_{o} (2.5 V - 0.6 V - 0.5 V_{o})

We know $K_{p} = 40 \cdot 40 μ A / V^{2} = 1600 μ A / V^{2}$ and $K_{n} = 20 \cdot 100 μ A / V^{2} = 2000 μ A / V^{2}$ , so equate the equations and get that:

V_{o} = 0.984 V

which satisfies that $V_{o} \in (0.6 V, 1.9 V)$ as needed. Plug this into our current equation to get the current:

I = I_{P 1} = 2770 μ A

7.23

A CMOS inverter has $V_{o} = V_{L}$ , where we sink a current of $1.5 mA$ and maintain $V_{L} \leq 0.6 V$ . When $V_{o} \geq V_{H}$ then the CMOS sources a current of $60 μ A$ , and maintains $V_{H} \geq 2.4 V$ . We'll find the minimum $W / L$ ratios of the NMOS and PMOS to meet this, using $V_{D D} = 5 V$ .

When we have $V_{o} = V_{L}$ , then the we have the $M_{P}$ as "on" and $M_{N}$ as "off", so $M_{N}$ is triode and $M_{P}$ is in saturation. We can just focus on the triode part, as it contains solving $V_{L}$ in there. We know here that $V_{H} = 5 V$ :

I_{n, t r i} = 1.5 mA \Rightarrow 1.5 mA = K_{n}^{'} \cdot (W / L)_{N} \cdot (\underset{V_{G S}}{\underset{⏟}{5 V - 0.6 V}} - 0.5 \cdot \underset{V_{D S}}{\underset{⏟}{V_{L}}}) V_{L}

we can use the maximum $V_{L}$ value as if we do then we can guarantee that we are always under that limit:

\Rightarrow (W / L)_{N} = 6.010 / 1

In a similar way, when we have $V_{o} = V_{H}$ then we have the opposite effect, where here $V_{S D} = 5 V - 2.4 V = 2.6 V$ and $V_{S G} = 5 V - 0.6 V = 4.4 V$ :

I_{p, t r i} = 60 μ A \Rightarrow 60 μ A = K_{p}^{'} \cdot (W / L)_{P} \cdot (5 V - 0.6 V - 0.5 \cdot 2.6 V) 2.6 V \Rightarrow (W / L)_{P} = 0.180 / 1 = \frac{1}{5.373}